Flash memories have revolutionized the way system designers store digital control code and data. Flash memory technology offers a unique combination of features, non-volatility, in-system reprogrammability, and high-density.
Its non-volatile nature allows for the data stored in the memory cells to be retained even without power. It is similar to an EEPROM in that it is electrically erasable. The differences being primarily in density and granularity. EEPROMs are usually smaller, and byte erasable/writable, whereas flash memory is usually bigger, and block erasable/writable (blocks are groups of bytes, usually in multiples like 4K, 16K, etc.). In this respect, erasing and writing whole blocks at a time make flash memories faster than EEPROMS.
However, flash memory is not without its difficulties. Due to its nature, only a limited number of write/erase cycles can be performed. That is, the devices will actually wear-out with repeated use. The very thin layers involved (especially the tunnel oxide) eventually lose their capability to retain a charge.
With increasing usage and subsequently higher cycle counts, a block's program and erase performance degrades because of the trapped charge in transistor oxides and other stress phenomena. Eventually, the entire block will become useless.
Other disadvantages of flash memories are that they are slow compared to RAM, especially on write and erase functions. Additionally, some devices allow small numbers of bad blocks, analogous to having a few bad sectors on a disk drive.
There are several variants to flash memory. The two most common types are NOR and NAND. These names refer to details of the internal transistor structure, and the internal differences result in corresponding behavioral differences. While there is some overlap, each of these architectures is best suited to different applications.
NOR flash memory is random accessible. The information it contains can be read, and re-read, in any sequence or order. This makes it well suited for code-storage applications. NOR architectures provide a parallel internal architecture which enables fast random access to any location within the array for reads.
NAND flash is sequentially accessible. The information it contains is read in sequence, one bit (or byte) following the next, in order. This makes it poorly-suited for code-storage applications, but is made-to-order for data or file storage applications. NAND internal architectures comprise rows of transistors connected together serially. The resultant random access time is comparatively longer than that of parallel-architecture flash memory, because the memory must first sequentially sense and transfer data within each cell in the row to an on-chip buffer. However, subsequent access within the buffer is as fast as that of a parallel-architecture memory.
The design of the flash memory incorporates the floating gate of the EEPROM and hot electron injection for the write process with Fowler-Nordheim tunneling for the erase process. The charge injection process removes or adds electrons from the floating gate. The floating gate provides a gate voltage similar to a single-gate transistor, providing logic ONEs or logic ZEROs. That is, when the floating gate is strongly programmed to a positive charge, the floating gate transistor's channel becomes highly conductive. This state corresponds to a binary digit, such as logic ONE. On the other hand, when the floating gate is strongly programmed to a negative charge, the cell becomes non-conductive. This state corresponds to a binary digit, such as a logic ZERO. The cell volume is about the size of an EPROM, and the chip layout involves the erase of a section on the chip (unlike the bit-by-bit erase of the EEPROM).
The two main techniques used to alter the data stored in a flash-memory cell are channel-hot-electron (CHE) injection and Fowler-Nordheim (FN) tunneling. In each case, an applied electric field adds or removes electron charge from the transistor's floating gate, changing the threshold voltage. A subsequent read at a consistent reference voltage turns on some transistors, which may result as a ONE or a ZERO at the memory output, and leaves off others. Both approaches use high voltages either from the outside world or from internal, on-chip charge pumps.
Some CHE-based flash memories draw electrons from the source junction, others from the drain. CHE places no significant stress on the oxide layer below the floating gate, ensuring high reliability through extended cycling. CHE shortcomings include fundamentally low-efficiency programming, which high internal voltages and electric fields sometimes overcome, with subsequent high current draw. Whereas write performance is not a primary concern for infrequently updated code, it is often crucial for data and file-storage applications.
All flash technologies use FN tunneling for erasing, and non-NOR technologies employ it for both programming and erasing. FN offers focused electron transfer; it directly adds or removes charges to or from the floating gate. This characteristic manifests itself as low-current programming and erasing, which enables high-efficiency and low-power operation, shrinking on-chip voltage pump size. Depending on the technology, FN electron tunneling occurs between the floating gate on one side, and the substrate, drain, source or optional erase gate on another.
Fowler-Nordheim tunneling, or field emission, is the process whereby electrons tunnel through a barrier in the presence of a high electric field. During the erase process, an erasing potential is applied in parallel to the entire array, or to large sectors of the array. The primary current in the erase process generated by this potential is this Fowler-Nordheim tunneling current, by which electrons are driven from the floating gate of the memory cell.
Another source of current during the erasing procedure is known as band-to-band tunneling. This results in current into the substrate (or source/drain), and current in the form of unwanted holes stay in an area about 15-30 Angstroms away from the surface of the silicon. Referring to FIG. 1, a conventional chip erase method is shown. Initially an erase timer 150 is started, step S1. Then, the A.sub.RVSS current pump path is turned on, step S2. Next, a query loop, step S3, is initiated, checking whether the erase timer 150 has expired. Step S3 continues until the result of this query is YES. At that time, the high voltage is discharged, step S4, and the chip erase method ends. Step S4 can be controlled by a timer or an internal circuit delay. Further, Since over erase is not of concern, there is no erase verification in the loop of FIG. 1.
It has been known, for example in Shiau et al., U.S. Pat. No. 5,699,298, that the use of a negative gate potential during the erase process allows use of a lower source voltage. The lower source voltage suppresses avalanche breakdown and improves endurance and reliability of the cell.
However, the band-to-band current is still about 10 nA per memory cell at the beginning of the erase operation when the cell is in a high threshold state. Thus, for a 2 Mb flash memory, erase transient current is about 20 mA at the beginning of a chip erase operation. For a single voltage source flash device, this high current is generated from a charge pump which can boost voltage but only has a limited current driving capability unless a very large pump capacitor is used in the design. Furthermore, for a low V.sub.CC (3.3V and lower) flash memory device, the problem is increasingly worse.
Thus, it would be desirable to reduce the transient erase current while maintaining the significant current driving capability of an on-chip charge pump.